SerDes IO Design Engineer - Apple, Inc (Austin, TX)
Job Summary In this highly visible role, you will Drive design and methodology of next generation Analog and SerDes IP designs.
This will include development of both system and circuit level IP.
Key Qualifications Very knowledgeable about the common high-speed serial data protocols Experience in analyzing link budget for high-speed serial links Good knowledge of different CDR architectures Good knowledge of Tx/Rx equalization techniques Experience in C/Matlab modelling of CDR loops Able to create block-level requirements from link budget analysis and models Good experience in lab testing of high-speed serial links and defining equipment needs Good knowledge of analog CMOS designs.
Able to create VerilogA/AMS behavioral models in Cadence.
Description Responsibilities include:
Linking budget for PHY Behavioral modeling of PHY to assess different architectures.
Transistor-level feasibility studies for various blocks in Rx/Tx/Clk generation Creating block-level specifications based on link-budget, behavioral modeling, and transistor-level feasibility Transistor-level design of PHY high-speed sub-blocks.
Driving mask design to implement layout view of designs Generation/QA of various IP Kit views/files.
Defining production/bench-level test plans Design for ESD compliance Education BSEE/MSEE is required Source:
.
Estimated Salary: $20 to $28 per hour based on qualifications.
This will include development of both system and circuit level IP.
Key Qualifications Very knowledgeable about the common high-speed serial data protocols Experience in analyzing link budget for high-speed serial links Good knowledge of different CDR architectures Good knowledge of Tx/Rx equalization techniques Experience in C/Matlab modelling of CDR loops Able to create block-level requirements from link budget analysis and models Good experience in lab testing of high-speed serial links and defining equipment needs Good knowledge of analog CMOS designs.
Able to create VerilogA/AMS behavioral models in Cadence.
Description Responsibilities include:
Linking budget for PHY Behavioral modeling of PHY to assess different architectures.
Transistor-level feasibility studies for various blocks in Rx/Tx/Clk generation Creating block-level specifications based on link-budget, behavioral modeling, and transistor-level feasibility Transistor-level design of PHY high-speed sub-blocks.
Driving mask design to implement layout view of designs Generation/QA of various IP Kit views/files.
Defining production/bench-level test plans Design for ESD compliance Education BSEE/MSEE is required Source:
.
Estimated Salary: $20 to $28 per hour based on qualifications.
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