Physical Design Timing Engineer
Job Details:
Job Description:
Performs timing analysis and timing optimization, generates, and verifies timing constraints, and fixes timing violations at IP/SOC level.
Other responsibilities include:
- Contribute to the I/O timing analysis and characterization at a prominent level.
- Generate I/O timing libs for various PVT corners for foundry and consistently support the customer queries.
- Working on static timing analysis setup and signoff of multi-corner multi-voltage designs.
Areas of focus include timing analysis, power estimation, extraction based characterization for foundational I/Os across internal and external foundry processes.
- Own timing execution to meet timing requirements including timing budgets, buffer planning, automatic constraints/exceptions generation and management, and other key differentiating capabilities for quality and efficient timing closure.
- Work closely with designers to understand the design and convergence challenges and provide ECOs without compromising on PPA optimization.
- Act as liaison between customers, design team and EDA teams to understand the intricacies of customer requests and communicate effectively.
#DesignEnablement
Qualifications:
Minimum qualifications are required to be initially considered for this position.
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum
Qualifications:
Candidate must possess a BS degree with 4
years of experience or MS degree with 3
years of experience or PhD degree with 1
years of experience in Electrical/Computer Engineering, Computer Science or related field.
4
years of experience in the following:
- Demonstrated experience in areas of Timing analysis, timing convergence, SI/Noise analysis, Signoff quality (PVT, process variation effects, guardbanding, etc), Timing ECOs, PV/Noise modelling,.
libs, is a must.
- Expertise in industry standard EDA tools (Primetime, Tempus) and ASIC design flow is required.
Preferred
Qualifications:
4
years of experience in the following:
- Multi-voltage scenarios design handling knowledge is expected.
- STA closure/convergence execution on I/O designs is preferred.
- Proficiency in scripting language, such as, Perl, Python and Tcl is an added advantage.
Job Type:
Experienced HireShift:
Shift 1 (United States of America)Primary Location:
US, Oregon, HillsboroAdditional Locations:
US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, AustinBusiness group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.
Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of TrustN/A
Benefits:
We offer a total compensation package that ranks among the best in the industry.
It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.
Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in US, California:
$123,419.
00-$185,123.
00Salary range dependent on a number of factors including location and experience.
Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs.
SummaryLocation:
US, Oregon, Hillsboro; US, California, Folsom; US, California, Santa Clara; US, Texas, Austin; US, Arizona, PhoenixType:
Full time.
Estimated Salary: $20 to $28 per hour based on qualifications.
Job Description:
Performs timing analysis and timing optimization, generates, and verifies timing constraints, and fixes timing violations at IP/SOC level.
Other responsibilities include:
- Contribute to the I/O timing analysis and characterization at a prominent level.
- Generate I/O timing libs for various PVT corners for foundry and consistently support the customer queries.
- Working on static timing analysis setup and signoff of multi-corner multi-voltage designs.
Areas of focus include timing analysis, power estimation, extraction based characterization for foundational I/Os across internal and external foundry processes.
- Own timing execution to meet timing requirements including timing budgets, buffer planning, automatic constraints/exceptions generation and management, and other key differentiating capabilities for quality and efficient timing closure.
- Work closely with designers to understand the design and convergence challenges and provide ECOs without compromising on PPA optimization.
- Act as liaison between customers, design team and EDA teams to understand the intricacies of customer requests and communicate effectively.
#DesignEnablement
Qualifications:
Minimum qualifications are required to be initially considered for this position.
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum
Qualifications:
Candidate must possess a BS degree with 4
years of experience or MS degree with 3
years of experience or PhD degree with 1
years of experience in Electrical/Computer Engineering, Computer Science or related field.
4
years of experience in the following:
- Demonstrated experience in areas of Timing analysis, timing convergence, SI/Noise analysis, Signoff quality (PVT, process variation effects, guardbanding, etc), Timing ECOs, PV/Noise modelling,.
libs, is a must.
- Expertise in industry standard EDA tools (Primetime, Tempus) and ASIC design flow is required.
Preferred
Qualifications:
4
years of experience in the following:
- Multi-voltage scenarios design handling knowledge is expected.
- STA closure/convergence execution on I/O designs is preferred.
- Proficiency in scripting language, such as, Perl, Python and Tcl is an added advantage.
Job Type:
Experienced HireShift:
Shift 1 (United States of America)Primary Location:
US, Oregon, HillsboroAdditional Locations:
US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, AustinBusiness group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.
Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of TrustN/A
Benefits:
We offer a total compensation package that ranks among the best in the industry.
It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.
Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in US, California:
$123,419.
00-$185,123.
00Salary range dependent on a number of factors including location and experience.
Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs.
SummaryLocation:
US, Oregon, Hillsboro; US, California, Folsom; US, California, Santa Clara; US, Texas, Austin; US, Arizona, PhoenixType:
Full time.
Estimated Salary: $20 to $28 per hour based on qualifications.
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