Senior Engineer - RTL Design at Samsung in Austin, TX
Position Summary Samsung is a world leader in Memory, LCD and System LSI technologies. We are currently looking for exceptional software and hardware talent to join our Samsung Austin R & D Center (SARC) in Austin, TX and our Advanced Computing Lab (ACL) in San Jose, CA. SARC was established in Austin, TX in 2010 to be one of Samsung's strategic investments in high performance low power ARM based device technology. Presently our GPU design teams, located in Austin (SARC) and San Jose (ACL), are developing a GPU that will be deployed in Samsung mobile products. Our System IP team located in Austin (SARC) is working on Coherent Interconnect and memory controller architectures.Role and Responsibilities We are looking for an RTL Design engineer to work as part of a custom DRAM memory controller IP team. This is an individual contributor role where the candidate will be tasked with driving the RTL design and performance/power optimization of various sub-blocks of the memory controller for the mobile market as well as other custom SoC markets. Architectural as well as RTL design experience is critical for success. Key responsibilities include:
Engage with other architects within the IP and at the SoC level to drive the architectural definition Partner with the physical design team to resolve implementation level details Work closely with design verification to test plan and otherwise ensure proper functionality Produce quality RTL on schedule meeting PPA goals Deliver quality micro-architectural level documentation Expect to collaborate with engineers in Korea on requirements Interact with GPU and other key IP to produce a good system level solution Skills and Qualifications Minimum requirements:
BSEE, Computer Engineer or comparable and 3
years of experience Demonstrated experience of successful Architectural through RTL design experience on various sub-blocks of high performance digital designs Good written and verbal communication skills Energetic, curious, self-driven Preferred candidate will possess the following:
Experience with DRAM technologies:
LPDDR4/5, DDR4/5, or similar Experience driving the RTL design of various sub-blocks of the memory controller for high performance digital designs Lower power design experience
Salary Range:
$80K -- $100K
Minimum Qualification
Electrical Engineering, Hardware DevelopmentEstimated Salary: $20 to $28 per hour based on qualifications.
Engage with other architects within the IP and at the SoC level to drive the architectural definition Partner with the physical design team to resolve implementation level details Work closely with design verification to test plan and otherwise ensure proper functionality Produce quality RTL on schedule meeting PPA goals Deliver quality micro-architectural level documentation Expect to collaborate with engineers in Korea on requirements Interact with GPU and other key IP to produce a good system level solution Skills and Qualifications Minimum requirements:
BSEE, Computer Engineer or comparable and 3
years of experience Demonstrated experience of successful Architectural through RTL design experience on various sub-blocks of high performance digital designs Good written and verbal communication skills Energetic, curious, self-driven Preferred candidate will possess the following:
Experience with DRAM technologies:
LPDDR4/5, DDR4/5, or similar Experience driving the RTL design of various sub-blocks of the memory controller for high performance digital designs Lower power design experience
Salary Range:
$80K -- $100K
Minimum Qualification
Electrical Engineering, Hardware DevelopmentEstimated Salary: $20 to $28 per hour based on qualifications.
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